Permanent URL to this publication: http://dx.doi.org/10.5167/uzh-17595
Fasnacht, D B; Whatley, A M; Indiveri, G (2008). A serial communication infrastructure for multi-chip address event systems. In: Institute of Electrical and Electronics Engineers, [et al.]. Proceedings of 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, WA, 18-21 May 2008. Piscataway, NJ, US, 648-651. ISBN 978-1-4244-1683-7.
In recent years there have been an increasing number of research groups that have begun to develop multi-chip address-event systems.
The communication protocol used to transmit signals between these systems' components is based on the Address-Event Representation (AER). It is therefore important to have access to robust and reliable AER communication infrastructures for streamlining the systems' development and prototyping stages. We propose an AER communication infrastructure that can be easily interfaced to workstations or laptops during a prototyping phase, and that can be embedded into compact and low-cost systems in the application phase. The infrastructure proposed uses a novel serial AER interface with flow-control, overcomes many of the drawbacks observed with previous solutions, and can achieve event rates of up to 78.125MHz for 32bit AEs.
|Item Type:||Book Section, refereed, original work|
|Communities & Collections:||07 Faculty of Science > Institute of Neuroinformatics|
|DDC:||570 Life sciences; biology|
|Deposited On:||06 Mar 2009 17:24|
|Last Modified:||09 Jul 2012 05:44|
|Publisher:||IEEE Service Center|
|Additional Information:||© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
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