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Permanent URL to this publication: http://dx.doi.org/10.5167/uzh-17619

Liu, S C; Möckel, R (2008). Temporally learning floating-gate VLSI synapses. In: IEEE. Proceedings of 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, WA, 18-21 May 2008. Piscataway, NJ, US: IEEE Service Center, 2154-2157.

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We present a floating-gate synaptic circuit that updates its weight according to the Spike-Timing-Dependent Plasticity (STDP) rule. The weight (or floating-gate voltage) is updated only if the time difference between the pre- and post-synaptic spikes falls within a learning window. The update is implemented through tunneling and injection mechanisms which can be tuned for very long time constants up to seconds. The novelty of this circuit is that the tunneling and injection mechanisms are turned on only when the correlation of the pre and postsynaptic activity is significant. The additional benefit of this non-volatile technology is that synaptic weights can be stored locally on chip. We present experimental results that show the learning and normalization effects from the fabricated circuits.


9 citations in Web of Science®
8 citations in Scopus®
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131 downloads since deposited on 06 Mar 2009
6 downloads since 12 months

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Additional indexing

Item Type:Book Section, refereed, original work
Communities & Collections:07 Faculty of Science > Institute of Neuroinformatics
Dewey Decimal Classification:570 Life sciences; biology
Deposited On:06 Mar 2009 15:56
Last Modified:05 Apr 2016 13:10
Publisher:IEEE Service Center
Additional Information:© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Publisher DOI:10.1109/ISCAS.2008.4541877

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