Permanent URL to this publication: http://dx.doi.org/10.5167/uzh-17619
Liu, S C; Möckel, R (2008). Temporally learning floating-gate VLSI synapses. In: Institute of Electrical and Electronics Engineers, [et al.]. Proceedings of 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, WA, 18-21 May 2008. Piscataway, NJ, US, 2154-2157. ISBN 978-1-4244-1683-7.
We present a floating-gate synaptic circuit that
updates its weight according to the Spike-Timing-Dependent Plasticity (STDP) rule. The weight (or floating-gate voltage) is updated only if the time difference between the pre- and post-synaptic spikes falls within a learning window. The update is implemented through tunneling and injection mechanisms which can be tuned for very long time constants up to seconds. The novelty of this circuit is that the tunneling and injection mechanisms are turned on only when the correlation of the pre and postsynaptic activity is significant. The additional benefit of this non-volatile technology is that synaptic weights can be stored locally on chip. We present experimental results that show the learning and normalization effects from the fabricated circuits.
|Item Type:||Book Section, refereed, original work|
|Communities & Collections:||07 Faculty of Science > Institute of Neuroinformatics|
|DDC:||570 Life sciences; biology|
|Deposited On:||06 Mar 2009 15:56|
|Last Modified:||09 Jul 2012 03:44|
|Publisher:||IEEE Service Center|
|Additional Information:||© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
Scopus®. Citation Count: 6
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