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Permanent URL to this publication: http://dx.doi.org/10.5167/uzh-32029

Linares-Barranco, A; Gomez-Rodriguez, F; Jimenez, G; Delbruck, T; Berner, R; Liu, S C (2009). Implementation of a time-warping AER mapper. In: IEEE International Symposium on Circuits and Systems, 2009 (ISCAS 2009), Taipei, Taiwan, 24 May 2009 - 27 May 2009, 2886-2889.

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Abstract

In the recent implementation of neuromorphic spike based sensors, multi-neuron processors and actuators, the spike traffic between devices is coded in the form of asynchronous spike streams following the Address-Event-Representation protocol. This spike information can be modified during the transmission from one device to another by using a mapper device. In this paper we present a mapper implementation that transforms event addresses and also can delay events in time. We discuss two different architectures for implementing the time delays on an FPGA board (USB-AER), and we present an
example of the use of the time delay feature in the mapper in the implementation of an visual elementary motion detection model using the spike outputs of a temporal contrast retina.

Item Type:Conference or Workshop Item (Speech), refereed, original work
Communities & Collections:07 Faculty of Science > Institute of Neuroinformatics
DDC:570 Life sciences; biology
Uncontrolled Keywords:spiking AER mapper
Language:English
Event End Date:27 May 2009
Deposited On:13 Mar 2010 10:26
Last Modified:09 Jul 2012 06:16
ISBN:978-1-4244-3827-3
Additional Information:© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Publisher DOI:10.1109/ISCAS.2009.5118405
Related URLs:http://conf.ncku.edu.tw/iscas2009/ (Organisation)
http://ieeexplore.ieee.org (Publisher)
http://www.ini.uzh.ch/node/20517
Citations:Google Scholar™

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