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A two-dimensional configurable active silicon dendritic neuron array


Wang, Y; Liu, S-C (2011). A two-dimensional configurable active silicon dendritic neuron array. IEEE Transactions on Circuits and Systems - Part I: Regular Papers, 58(9):2159-2171.

Abstract

This paper presents a 2-D programmable dendritic neuron array consisting of a 3 x 32 dendritic compartment array and a 1 x 32 somatic compartment array. Each dendritic compartment contains two types of regenerative nonlinearities: a NMDA synaptic nonlinearity and a dendritic spike nonlinearity. The chip supports the programmability of local synaptic weights and the configuration of dendritic morphology for individual neurons through the address-event representation protocol. Neurons can be stimulated and recorded using the same protocol. A novel local cable circuit between neighboring compartments allows one to construct different dendritic morphologies. This chip provides a hardware platform for studying the network behavior of neurons with active dendrites and for investigating the role of different dendritic morphologies in neuronal computation. Based on experimental results from a chip fabricated in a 4-metal, 2-poly, 0.35 mu m CMOS technology, this work shows one instance of how dendritic nonlinearities can contribute to neuronal computation, that is, the dendritic spike mechanism can dynamically reduce the mismatch-induced coefficient of variation of the somatic response amplitude from about 40% to 3.5%, and the response timing jitter by a factor of 2.

This paper presents a 2-D programmable dendritic neuron array consisting of a 3 x 32 dendritic compartment array and a 1 x 32 somatic compartment array. Each dendritic compartment contains two types of regenerative nonlinearities: a NMDA synaptic nonlinearity and a dendritic spike nonlinearity. The chip supports the programmability of local synaptic weights and the configuration of dendritic morphology for individual neurons through the address-event representation protocol. Neurons can be stimulated and recorded using the same protocol. A novel local cable circuit between neighboring compartments allows one to construct different dendritic morphologies. This chip provides a hardware platform for studying the network behavior of neurons with active dendrites and for investigating the role of different dendritic morphologies in neuronal computation. Based on experimental results from a chip fabricated in a 4-metal, 2-poly, 0.35 mu m CMOS technology, this work shows one instance of how dendritic nonlinearities can contribute to neuronal computation, that is, the dendritic spike mechanism can dynamically reduce the mismatch-induced coefficient of variation of the somatic response amplitude from about 40% to 3.5%, and the response timing jitter by a factor of 2.

Citations

3 citations in Web of Science®
3 citations in Scopus®
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Additional indexing

Item Type:Journal Article, refereed, original work
Communities & Collections:07 Faculty of Science > Institute of Neuroinformatics
Dewey Decimal Classification:570 Life sciences; biology
Uncontrolled Keywords:Active mechanisms;Analog-digital integrated circuits;Biological neural networks;Dendrite;Hardware;Multi-layer neural network;Spatiotemporal processing
Date:1 September 2011
Deposited On:05 Mar 2012 15:23
Last Modified:05 Apr 2016 15:42
Publisher:IEEE
Series Name:IEEE transactions on circuits and systems. I, Regular papers
Number of Pages:12
ISSN:1057-7122
Publisher DOI:10.1109/TCSI.2011.2112570

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