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This paper presents a 2-D programmable dendritic neuron array consisting of a 3 x 32 dendritic compartment array and a 1 x 32 somatic compartment array. Each dendritic compartment contains two types of regenerative nonlinearities: a NMDA synaptic nonlinearity and a dendritic spike nonlinearity. The chip supports the programmability of local synaptic weights and the configuration of dendritic morphology for individual neurons through the address-event representation protocol. Neurons can be stimulated and recorded using the same protocol. A novel local cable circuit between neighboring compartments allows one to construct different dendritic morphologies. This chip provides a hardware platform for studying the network behavior of neurons with active dendrites and for investigating the role of different dendritic morphologies in neuronal computation. Based on experimental results from a chip fabricated in a 4-metal, 2-poly, 0.35 mu m CMOS technology, this work shows one instance of how dendritic nonlinearities can contribute to neuronal computation, that is, the dendritic spike mechanism can dynamically reduce the mismatch-induced coefficient of variation of the somatic response amplitude from about 40% to 3.5%, and the response timing jitter by a factor of 2.
|Item Type:||Journal Article, refereed, original work|
|Communities & Collections:||07 Faculty of Science > Institute of Neuroinformatics|
|DDC:||570 Life sciences; biology|
|Uncontrolled Keywords:||Active mechanisms;Analog-digital integrated circuits;Biological neural networks;Dendrite;Hardware;Multi-layer neural network;Spatiotemporal processing|
|Date:||01 September 2011|
|Deposited On:||05 Mar 2012 16:23|
|Last Modified:||23 Nov 2012 16:11|
|Series Name:||IEEE transactions on circuits and systems. I, Regular papers|
|Number of Pages:||12|
|WoS Citation Count:||0|
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