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A PCI based high-fanout AER mapper with 2 GiB RAM look-up table, 0.8 µs latency and 66MHz output event-rate


Fasnacht, D B; Indiveri, G (2011). A PCI based high-fanout AER mapper with 2 GiB RAM look-up table, 0.8 µs latency and 66MHz output event-rate. In: 45th Annual Conference on Information Sciences and Systems 2011, Baltimore, MD, 23 March 2011 - 25 March 2011, 1-6.

Abstract

Neuromorphic systems have been increasing in size and complexity in recent years, thanks also the adoption of the Address-Event Representation (AER) as a standard for transmitting signals among chips, and building multi-chip event-based systems. AER mapper devices that route Address-Events from multiple sources to different multiple destinations are crucial components of these systems, as they allow users to flexibly compose multi-chip setups, re-configure them, and program different architecture or network topologies. In this paper we present a PCI based high-fanout AER mapper with 2 GiB RAM look-up table, 0.8 μs latency and 66 MHz output event-rate. Integrated with a PC it forms a very flexible and affordable AER experimental platform which is suitable for prototyping and research projects. Indeed, multiple instances of this system are already being used to perform various types of AER experiments. In addition, the system's ability to implement probabilistic address-event mappings further extends the range of experiments that can be performed using this platform. We describe the hardware system implementation details, compare our approach to previously proposed ones, and present experimental results which demonstrate how the system provides optimal performance for experiments with high average fanout and how for low fanout mappings the limiting factor is given by the 0.8 μs latency induced by the PC on each random memory access.

Neuromorphic systems have been increasing in size and complexity in recent years, thanks also the adoption of the Address-Event Representation (AER) as a standard for transmitting signals among chips, and building multi-chip event-based systems. AER mapper devices that route Address-Events from multiple sources to different multiple destinations are crucial components of these systems, as they allow users to flexibly compose multi-chip setups, re-configure them, and program different architecture or network topologies. In this paper we present a PCI based high-fanout AER mapper with 2 GiB RAM look-up table, 0.8 μs latency and 66 MHz output event-rate. Integrated with a PC it forms a very flexible and affordable AER experimental platform which is suitable for prototyping and research projects. Indeed, multiple instances of this system are already being used to perform various types of AER experiments. In addition, the system's ability to implement probabilistic address-event mappings further extends the range of experiments that can be performed using this platform. We describe the hardware system implementation details, compare our approach to previously proposed ones, and present experimental results which demonstrate how the system provides optimal performance for experiments with high average fanout and how for low fanout mappings the limiting factor is given by the 0.8 μs latency induced by the PC on each random memory access.

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Additional indexing

Item Type:Conference or Workshop Item (Paper), refereed, original work
Communities & Collections:07 Faculty of Science > Institute of Neuroinformatics
Dewey Decimal Classification:570 Life sciences; biology
Language:English
Event End Date:25 March 2011
Deposited On:09 Mar 2012 14:18
Last Modified:05 Apr 2016 15:43
Publisher:IEEE
ISBN:978-1-4244-9847-5
Publisher DOI:10.1109/CISS.2011.5766102
Permanent URL: http://doi.org/10.5167/uzh-60760

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