Given the resurgent attractiveness of single-instruction-multiple-data (SIMD) processing, it is important for high-performance computing applications
to be SIMD-capable. The Hartree–Fock SCF (HF-SCF) application, in it’s canonical form, cannot fully exploit SIMD processing. Prior
attempts to implement Electron Repulsion Integral (ERI) sorting functionality to essentially “SIMD-ify” the HF-SCF application have met frustration
because of the low throughput of the sorting functionality. With greater awareness of computer architecture, we discuss how the sorting
functionality may be practically implemented to provide high-performance. Overall system performance analysis, including memory locality
analysis, is also conducted, and further emphasises that a system with ERI sorting is capable of very high throughput. We discuss two alternative
implementation options, with one immediately accessible software-based option discussed in detail. The impact of workload characteristics on
expected performance is also discussed, and it is found that in general as basis set size increases the potential performance of the system also
increases. Consideration is given to conventional CPUs, GPUs, FPGAs, and the Cell Broadband Engine architecture.
© 2008 Elsevier B.V. All rights reserved.