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A high-PDE, backside-illuminated SPAD in 65/40-nm 3D IC CMOS pixel with cascoded passive quenching and active recharge


Lindner, Scott; Pellegrini, Sara; Henrion, Yann; Rae, Bruce; Wolf, Martin; Charbon, Edoardo (2017). A high-PDE, backside-illuminated SPAD in 65/40-nm 3D IC CMOS pixel with cascoded passive quenching and active recharge. IEEE Electron Device Letters, 38(11):1547-1550.

Abstract

We present a complete pixel based on a single-photon avalanche diode (SPAD) fabricated in a backside-illuminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65-nm image sensor technology and a data processing tier in 40-nm CMOS. Using a simple, CMOS-compatible technique, the pixel is capable of passive quenching and active recharge at voltages well above those imposed by a single transistor whilst ensuring that the reliability limits across the gate-source (VGS), gate-drain (VGD) and drain- source (VDS) are not exceeded for any device. For a given technology, the circuit extends the maximum excess bias that SPADs can be operated at when using transistors as quenching elements, thus improving the SPAD sensitivity, timing performance, and photon detection probability uniformity. Implemented with 2.5-V thick oxide transistors and operated at 4.4-V excess bias, the design achieves a timing jitter of 95-ps full-width at half maximum, maximum photon detection efficiency (PDE) of 21.9% at 660 nm and 0.08% afterpulsing probabilitywith a dead time of 8 ns. This is both the lowest afterpulsing probability at 8-ns dead time and the highest peak PDE for a BSI SPAD in a 3D IC technology to date.

Abstract

We present a complete pixel based on a single-photon avalanche diode (SPAD) fabricated in a backside-illuminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65-nm image sensor technology and a data processing tier in 40-nm CMOS. Using a simple, CMOS-compatible technique, the pixel is capable of passive quenching and active recharge at voltages well above those imposed by a single transistor whilst ensuring that the reliability limits across the gate-source (VGS), gate-drain (VGD) and drain- source (VDS) are not exceeded for any device. For a given technology, the circuit extends the maximum excess bias that SPADs can be operated at when using transistors as quenching elements, thus improving the SPAD sensitivity, timing performance, and photon detection probability uniformity. Implemented with 2.5-V thick oxide transistors and operated at 4.4-V excess bias, the design achieves a timing jitter of 95-ps full-width at half maximum, maximum photon detection efficiency (PDE) of 21.9% at 660 nm and 0.08% afterpulsing probabilitywith a dead time of 8 ns. This is both the lowest afterpulsing probability at 8-ns dead time and the highest peak PDE for a BSI SPAD in a 3D IC technology to date.

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Additional indexing

Item Type:Journal Article, refereed, original work
Communities & Collections:04 Faculty of Medicine > University Hospital Zurich > Clinic for Neonatology
Dewey Decimal Classification:610 Medicine & health
Language:English
Date:22 September 2017
Deposited On:05 Jan 2018 19:15
Last Modified:19 Feb 2018 10:03
Publisher:Institute of Electrical and Electronics Engineers
ISSN:0741-3106
OA Status:Closed
Publisher DOI:https://doi.org/10.1109/LED.2017.2755989

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