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Computing spike-based convolutions on GPUs


Nageswaran, J M; Dutt, N; Wang, Y; Delbrueck, T (2009). Computing spike-based convolutions on GPUs. In: IEEE International Symposium on Circuits and Systems, 2009 (ISCAS 2009), Taipei, Taiwan, 24 May 2009 - 27 May 2009, 1917-1920.

Abstract

In spiking neural networks, asynchronous spike events are processed in parallel by neurons. Emulations of such networks are traditionally computed by CPUs or realized using dedicated neuromorphic hardware. In many neuromorphic systems, the address-event-representation (AER) is used for spike communication. In this paper we present the acceleration of AER based spike processing using a graphics processing unit (GPU). In our experiment we interface a 128times128 pixel AER vision sensor to a spiking neural network implemented on a GPU for real-time convolution-based nonlinear feature extraction with convolution kernel sizes ranging from 48times48 to 112times112 pixels. We show parallelism-performance trade-offs on GPUs for single spike per thread, multiple spikes per thread, and multiple objects parallelism techniques. Our implementation can achieve a kernel speedup of up to 35times on a single NVIDIA GTX280 board when compared to a CPU-only implementation.

Abstract

In spiking neural networks, asynchronous spike events are processed in parallel by neurons. Emulations of such networks are traditionally computed by CPUs or realized using dedicated neuromorphic hardware. In many neuromorphic systems, the address-event-representation (AER) is used for spike communication. In this paper we present the acceleration of AER based spike processing using a graphics processing unit (GPU). In our experiment we interface a 128times128 pixel AER vision sensor to a spiking neural network implemented on a GPU for real-time convolution-based nonlinear feature extraction with convolution kernel sizes ranging from 48times48 to 112times112 pixels. We show parallelism-performance trade-offs on GPUs for single spike per thread, multiple spikes per thread, and multiple objects parallelism techniques. Our implementation can achieve a kernel speedup of up to 35times on a single NVIDIA GTX280 board when compared to a CPU-only implementation.

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Additional indexing

Item Type:Conference or Workshop Item (Speech), refereed, original work
Communities & Collections:07 Faculty of Science > Institute of Neuroinformatics
Dewey Decimal Classification:570 Life sciences; biology
Language:English
Event End Date:27 May 2009
Deposited On:13 Mar 2010 11:00
Last Modified:07 Dec 2017 01:27
ISBN:978-1-4244-3827-3
Additional Information:© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Publisher DOI:https://doi.org/10.1109/ISCAS.2009.5118157
Related URLs:http://conf.ncku.edu.tw/iscas2009/ (Organisation)
http://ieeexplore.ieee.org (Publisher)
http://www.ini.uzh.ch/node/24220

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