Header

UZH-Logo

Maintenance Infos

Exploiting device mismatch in neuromorphic VLSI systems to implement axonal delays


Sheik, Sadique; Chicca, Elisabetta; Indiveri, Giacomo (2012). Exploiting device mismatch in neuromorphic VLSI systems to implement axonal delays. In: IEEE International Joint Conference on Neural Networks (IJCNN) 2012, Brisbane, Australia, 10 June 2012 - 15 June 2012, 1-6.

Abstract

Axonal delays are used in neural computation to implement faithful models of biological neural systems, and in spiking neural networks models to solve computationally demanding tasks. While there is an increasing number of software simulations of spiking neural networks that make use of axonal delays, only a small fraction of currently existing hardware neuromorphic systems supports them. In this paper we demonstrate a strategy to implement temporal delays in hardware spiking neural networks distributed across multiple Very Large Scale Integration (VLSI) chips. This is achieved by exploiting the inherent device mismatch present in the analog circuits that implement silicon neurons and synapses inside the chips, and the digital communication infrastructure used to configure the network topology and transmit the spikes across chips. We present an example of a recurrent VLSI spiking neural network that employs axonal delays and demonstrate how the proposed strategy efficiently implements them in hardware.

Abstract

Axonal delays are used in neural computation to implement faithful models of biological neural systems, and in spiking neural networks models to solve computationally demanding tasks. While there is an increasing number of software simulations of spiking neural networks that make use of axonal delays, only a small fraction of currently existing hardware neuromorphic systems supports them. In this paper we demonstrate a strategy to implement temporal delays in hardware spiking neural networks distributed across multiple Very Large Scale Integration (VLSI) chips. This is achieved by exploiting the inherent device mismatch present in the analog circuits that implement silicon neurons and synapses inside the chips, and the digital communication infrastructure used to configure the network topology and transmit the spikes across chips. We present an example of a recurrent VLSI spiking neural network that employs axonal delays and demonstrate how the proposed strategy efficiently implements them in hardware.

Statistics

Citations

Altmetrics

Additional indexing

Item Type:Conference or Workshop Item (Speech), refereed, original work
Communities & Collections:07 Faculty of Science > Institute of Neuroinformatics
Dewey Decimal Classification:570 Life sciences; biology
Language:English
Event End Date:15 June 2012
Deposited On:28 Feb 2013 08:28
Last Modified:07 Dec 2017 20:20
Publisher:IEEE
Series Name:Proceedings of the International Joint Conference on Neural Networks
Number of Pages:6
ISSN:2161-4393
ISBN:978-1-4673-1489-3
Publisher DOI:https://doi.org/10.1109/IJCNN.2012.6252636

Download

Full text not available from this repository.
View at publisher