Publication:

Minitaur, an event-driven FPGA-based spiking network accelerator

Date

Date

Date
2014
Journal Article
Published version

Citations

Citation copied

Neil, D., & Liu, S.-C. (2014). Minitaur, an event-driven FPGA-based spiking network accelerator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22, 2621–2628. https://doi.org/10.1109/TVLSI.2013.2294916

Abstract

Abstract

Abstract

Current neural networks are accumulating accolades for their performance on a variety of real-world computational tasks including recognition, classification, regression, and prediction, yet there are few scalable architectures that have emerged to address the challenges posed by their computation. This paper introduces Minitaur, an event-driven neural network accelerator, which is designed for low power and high performance. As an field-programmable gate array-based system, it can be integrated into existing robotics or it can offloa

Metrics

Views

160 since deposited on 2015-02-25
Acq. date: 2025-11-12

Additional indexing

Creators (Authors)

  • Neil, Daniel
    affiliation.icon.alt
  • Liu, Shih-Chii
    affiliation.icon.alt

Journal/Series Title

Journal/Series Title

Journal/Series Title

Volume

Volume

Volume
22

Page range/Item number

Page range/Item number

Page range/Item number
2621

Page end

Page end

Page end
2628

Item Type

Item Type

Item Type
Journal Article

Dewey Decimal Classifikation

Dewey Decimal Classifikation

Dewey Decimal Classifikation

Language

Language

Language
English

Publication date

Publication date

Publication date
2014

Date available

Date available

Date available
2015-02-25

ISSN or e-ISSN

ISSN or e-ISSN

ISSN or e-ISSN
1063-8210

OA Status

OA Status

OA Status
Closed

Free Access at

Free Access at

Free Access at
Unspecified

Metrics

Views

160 since deposited on 2015-02-25
Acq. date: 2025-11-12

Citations

Citation copied

Neil, D., & Liu, S.-C. (2014). Minitaur, an event-driven FPGA-based spiking network accelerator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22, 2621–2628. https://doi.org/10.1109/TVLSI.2013.2294916

Closed
Loading...
Thumbnail Image

Permanent URL

Permanent URL

Permanent URL
No files available