Publication:

Mapping Spiking Neural Networks to Neuromorphic Hardware

Date

Date

Date
2020
Journal Article
Published version
cris.lastimport.scopus2025-06-02T03:40:56Z
cris.lastimport.wos2025-07-22T01:31:08Z
cris.virtual.orcidhttps://orcid.org/0000-0002-7109-1689
cris.virtualsource.orcidc37c33aa-eed7-48a2-8196-ce4462cbaec4
dc.contributor.institutionUniversity of Zurich
dc.date.accessioned2020-02-14T09:50:09Z
dc.date.available2020-02-14T09:50:09Z
dc.date.issued2020-01-01
dc.description.abstract

Neuromorphic hardware implements biological neurons and synapses to execute a spiking neural network (SNN)-based machine learning. We present SpiNeMap, a design methodology to map SNNs to crossbar-based neuromorphic hardware, minimizing spike latency and energy consumption. SpiNeMap operates in two steps: SpiNeCluster and SpiNePlacer. SpiNeCluster is a heuristic-based clustering technique to partition an SNN into clusters of synapses, where intracluster local synapses are mapped within crossbars of the hardware and intercluster global synapses are mapped to the shared interconnect. SpiNeCluster minimizes the number of spikes on global synapses, which reduces spike congestion and improves application performance. SpiNePlacer then finds the best placement of local and global synapses on the hardware using a metaheuristic-based approach to minimize energy consumption and spike latency. We evaluate SpiNeMap using synthetic and realistic SNNs on a state-of-the-art neuromorphic hardware. We show that SpiNeMap reduces average energy consumption by 45% and spike latency by 21%, compared to the best-performing SNN mapping technique.

dc.identifier.doi10.1109/tvlsi.2019.2951493
dc.identifier.issn1063-8210
dc.identifier.scopus2-s2.0-85077296614
dc.identifier.urihttps://www.zora.uzh.ch/handle/20.500.14742/167788
dc.identifier.wos000506608100008
dc.language.isoeng
dc.subjectHardware and Architecture
dc.subjectElectrical and Electronic Engineering
dc.subjectSoftware
dc.subject.ddc570 Life sciences; biology
dc.title

Mapping Spiking Neural Networks to Neuromorphic Hardware

dc.typearticle
dcterms.accessRightsinfo:eu-repo/semantics/closedAccess
dcterms.bibliographicCitation.journaltitleIEEE Transactions on Very Large Scale Integration (VLSI) Systems
dcterms.bibliographicCitation.number1
dcterms.bibliographicCitation.originalpublishernameInstitute of Electrical and Electronics Engineers
dcterms.bibliographicCitation.pageend86
dcterms.bibliographicCitation.pagestart76
dcterms.bibliographicCitation.volume28
dspace.entity.typePublicationen
uzh.contributor.affiliationDrexel University
uzh.contributor.affiliationInteruniversity Micro-Electronics Center at Leuven
uzh.contributor.affiliationDrexel University
uzh.contributor.affiliationStichting IMEC Nederland
uzh.contributor.affiliationStichting IMEC Nederland
uzh.contributor.affiliationStichting IMEC Nederland
uzh.contributor.affiliationUniversity of Zurich
uzh.contributor.affiliationUniversity of California, Irvine
uzh.contributor.affiliationUniversity of California, Irvine
uzh.contributor.affiliationStichting IMEC Nederland
uzh.contributor.authorBalaji, Adarsha
uzh.contributor.authorCatthoor, Francky
uzh.contributor.authorDas, Anup
uzh.contributor.authorWu, Yuefeng
uzh.contributor.authorHuynh, Khanh
uzh.contributor.authorDell'Anna, Francesco G
uzh.contributor.authorIndiveri, Giacomo
uzh.contributor.authorKrichmar, Jeffrey L
uzh.contributor.authorDutt, Nikil D
uzh.contributor.authorSchaafsma, Siebren
uzh.contributor.correspondenceNo
uzh.contributor.correspondenceNo
uzh.contributor.correspondenceYes
uzh.contributor.correspondenceNo
uzh.contributor.correspondenceNo
uzh.contributor.correspondenceNo
uzh.contributor.correspondenceNo
uzh.contributor.correspondenceNo
uzh.contributor.correspondenceNo
uzh.contributor.correspondenceNo
uzh.document.availabilitynone
uzh.eprint.datestamp2020-02-14 09:50:09
uzh.eprint.lastmod2025-07-22 01:36:20
uzh.eprint.statusChange2020-02-14 09:50:09
uzh.harvester.ethYes
uzh.harvester.nbNo
uzh.identifier.doi10.5167/uzh-184171
uzh.jdb.eprintsId36108
uzh.oastatus.unpaywallhybrid
uzh.oastatus.zoraClosed
uzh.publication.citationBalaji, Adarsha; Catthoor, Francky; Das, Anup; Wu, Yuefeng; Huynh, Khanh; Dell'Anna, Francesco G; Indiveri, Giacomo; Krichmar, Jeffrey L; Dutt, Nikil D; Schaafsma, Siebren (2020). Mapping Spiking Neural Networks to Neuromorphic Hardware. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(1):76-86.
uzh.publication.originalworkoriginal
uzh.publication.publishedStatusfinal
uzh.scopus.impact107
uzh.scopus.subjectsSoftware
uzh.scopus.subjectsHardware and Architecture
uzh.scopus.subjectsElectrical and Electronic Engineering
uzh.workflow.doajuzh.workflow.doaj.false
uzh.workflow.eprintid184171
uzh.workflow.fulltextStatusrestricted
uzh.workflow.revisions59
uzh.workflow.rightsCheckkeininfo
uzh.workflow.sourceCrossRef:10.1109/tvlsi.2019.2951493
uzh.workflow.statusarchive
uzh.wos.impact80
Files

Original bundle

Name:
08913677.pdf
Size:
4.23 MB
Format:
Adobe Portable Document Format
Downloadable by admins only
Publication available in collections: