Publication: Mapping Spiking Neural Networks to Neuromorphic Hardware
Mapping Spiking Neural Networks to Neuromorphic Hardware
Date
Date
Date
| cris.lastimport.scopus | 2025-06-02T03:40:56Z | |
| cris.lastimport.wos | 2025-07-22T01:31:08Z | |
| cris.virtual.orcid | https://orcid.org/0000-0002-7109-1689 | |
| cris.virtualsource.orcid | c37c33aa-eed7-48a2-8196-ce4462cbaec4 | |
| dc.contributor.institution | University of Zurich | |
| dc.date.accessioned | 2020-02-14T09:50:09Z | |
| dc.date.available | 2020-02-14T09:50:09Z | |
| dc.date.issued | 2020-01-01 | |
| dc.description.abstract | Neuromorphic hardware implements biological neurons and synapses to execute a spiking neural network (SNN)-based machine learning. We present SpiNeMap, a design methodology to map SNNs to crossbar-based neuromorphic hardware, minimizing spike latency and energy consumption. SpiNeMap operates in two steps: SpiNeCluster and SpiNePlacer. SpiNeCluster is a heuristic-based clustering technique to partition an SNN into clusters of synapses, where intracluster local synapses are mapped within crossbars of the hardware and intercluster global synapses are mapped to the shared interconnect. SpiNeCluster minimizes the number of spikes on global synapses, which reduces spike congestion and improves application performance. SpiNePlacer then finds the best placement of local and global synapses on the hardware using a metaheuristic-based approach to minimize energy consumption and spike latency. We evaluate SpiNeMap using synthetic and realistic SNNs on a state-of-the-art neuromorphic hardware. We show that SpiNeMap reduces average energy consumption by 45% and spike latency by 21%, compared to the best-performing SNN mapping technique. | |
| dc.identifier.doi | 10.1109/tvlsi.2019.2951493 | |
| dc.identifier.issn | 1063-8210 | |
| dc.identifier.scopus | 2-s2.0-85077296614 | |
| dc.identifier.uri | https://www.zora.uzh.ch/handle/20.500.14742/167788 | |
| dc.identifier.wos | 000506608100008 | |
| dc.language.iso | eng | |
| dc.subject | Hardware and Architecture | |
| dc.subject | Electrical and Electronic Engineering | |
| dc.subject | Software | |
| dc.subject.ddc | 570 Life sciences; biology | |
| dc.title | Mapping Spiking Neural Networks to Neuromorphic Hardware | |
| dc.type | article | |
| dcterms.accessRights | info:eu-repo/semantics/closedAccess | |
| dcterms.bibliographicCitation.journaltitle | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | |
| dcterms.bibliographicCitation.number | 1 | |
| dcterms.bibliographicCitation.originalpublishername | Institute of Electrical and Electronics Engineers | |
| dcterms.bibliographicCitation.pageend | 86 | |
| dcterms.bibliographicCitation.pagestart | 76 | |
| dcterms.bibliographicCitation.volume | 28 | |
| dspace.entity.type | Publication | en |
| uzh.contributor.affiliation | Drexel University | |
| uzh.contributor.affiliation | Interuniversity Micro-Electronics Center at Leuven | |
| uzh.contributor.affiliation | Drexel University | |
| uzh.contributor.affiliation | Stichting IMEC Nederland | |
| uzh.contributor.affiliation | Stichting IMEC Nederland | |
| uzh.contributor.affiliation | Stichting IMEC Nederland | |
| uzh.contributor.affiliation | University of Zurich | |
| uzh.contributor.affiliation | University of California, Irvine | |
| uzh.contributor.affiliation | University of California, Irvine | |
| uzh.contributor.affiliation | Stichting IMEC Nederland | |
| uzh.contributor.author | Balaji, Adarsha | |
| uzh.contributor.author | Catthoor, Francky | |
| uzh.contributor.author | Das, Anup | |
| uzh.contributor.author | Wu, Yuefeng | |
| uzh.contributor.author | Huynh, Khanh | |
| uzh.contributor.author | Dell'Anna, Francesco G | |
| uzh.contributor.author | Indiveri, Giacomo | |
| uzh.contributor.author | Krichmar, Jeffrey L | |
| uzh.contributor.author | Dutt, Nikil D | |
| uzh.contributor.author | Schaafsma, Siebren | |
| uzh.contributor.correspondence | No | |
| uzh.contributor.correspondence | No | |
| uzh.contributor.correspondence | Yes | |
| uzh.contributor.correspondence | No | |
| uzh.contributor.correspondence | No | |
| uzh.contributor.correspondence | No | |
| uzh.contributor.correspondence | No | |
| uzh.contributor.correspondence | No | |
| uzh.contributor.correspondence | No | |
| uzh.contributor.correspondence | No | |
| uzh.document.availability | none | |
| uzh.eprint.datestamp | 2020-02-14 09:50:09 | |
| uzh.eprint.lastmod | 2025-07-22 01:36:20 | |
| uzh.eprint.statusChange | 2020-02-14 09:50:09 | |
| uzh.harvester.eth | Yes | |
| uzh.harvester.nb | No | |
| uzh.identifier.doi | 10.5167/uzh-184171 | |
| uzh.jdb.eprintsId | 36108 | |
| uzh.oastatus.unpaywall | hybrid | |
| uzh.oastatus.zora | Closed | |
| uzh.publication.citation | Balaji, Adarsha; Catthoor, Francky; Das, Anup; Wu, Yuefeng; Huynh, Khanh; Dell'Anna, Francesco G; Indiveri, Giacomo; Krichmar, Jeffrey L; Dutt, Nikil D; Schaafsma, Siebren (2020). Mapping Spiking Neural Networks to Neuromorphic Hardware. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(1):76-86. | |
| uzh.publication.originalwork | original | |
| uzh.publication.publishedStatus | final | |
| uzh.scopus.impact | 107 | |
| uzh.scopus.subjects | Software | |
| uzh.scopus.subjects | Hardware and Architecture | |
| uzh.scopus.subjects | Electrical and Electronic Engineering | |
| uzh.workflow.doaj | uzh.workflow.doaj.false | |
| uzh.workflow.eprintid | 184171 | |
| uzh.workflow.fulltextStatus | restricted | |
| uzh.workflow.revisions | 59 | |
| uzh.workflow.rightsCheck | keininfo | |
| uzh.workflow.source | CrossRef:10.1109/tvlsi.2019.2951493 | |
| uzh.workflow.status | archive | |
| uzh.wos.impact | 80 | |
| Files | Original bundle
08913677.pdfview file |Download4.23 MB | |
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