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Minitaur, an event-driven FPGA-based spiking network accelerator

Neil, Daniel; Liu, Shih-Chii (2014). Minitaur, an event-driven FPGA-based spiking network accelerator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(12):2621-2628.

Abstract

Current neural networks are accumulating accolades for their performance on a variety of real-world computational tasks including recognition, classification, regression, and prediction, yet there are few scalable architectures that have emerged to address the challenges posed by their computation. This paper introduces Minitaur, an event-driven neural network accelerator, which is designed for low power and high performance. As an field-programmable gate array-based system, it can be integrated into existing robotics or it can offload computationally expensive neural network tasks from the CPU. The version presented here implements a spiking deep network which achieves 19 million postsynaptic currents per second on 1.5 W of power and supports up to 65 K neurons per board. The system records 92% accuracy on the MNIST handwritten digit classification and 71% accuracy on the 20 newsgroups classification data set. Due to its event-driven nature, it allows for trading off between accuracy and latency.

Additional indexing

Item Type:Journal Article, not_refereed, original work
Communities & Collections:07 Faculty of Science > Institute of Neuroinformatics
Dewey Decimal Classification:570 Life sciences; biology
Scopus Subject Areas:Physical Sciences > Software
Physical Sciences > Hardware and Architecture
Physical Sciences > Electrical and Electronic Engineering
Language:English
Date:2014
Deposited On:25 Feb 2015 10:26
Last Modified:12 Mar 2025 02:41
Publisher:Institute of Electrical and Electronics Engineers
Number of Pages:1
ISSN:1063-8210
OA Status:Closed
Publisher DOI:https://doi.org/10.1109/TVLSI.2013.2294916
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