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On-Chip ID Generation for Multi-Node Implantable Devices Using SA-PUF

Gao, Chang; Ghoreishizadeh, Sara; Liu, Yan; Constandinou, Timothy (2017). On-Chip ID Generation for Multi-Node Implantable Devices Using SA-PUF. In: IEEE International Symposium on Circuits and Systems (ISCAS) 2017, Baltimore, USA, 29 May 2017 - 6 January 2017, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 2017.

Abstract

This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 μm CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.

Additional indexing

Item Type:Conference or Workshop Item (Paper), refereed, original work
Communities & Collections:07 Faculty of Science > Institute of Neuroinformatics
Dewey Decimal Classification:570 Life sciences; biology
Scopus Subject Areas:Physical Sciences > Electrical and Electronic Engineering
Language:English
Event End Date:6 January 2017
Deposited On:23 Feb 2018 09:44
Last Modified:26 Jan 2022 16:12
Publisher:Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 2017
Series Name:IEEE International Symposium on Circuits and Systems (ISCAS)
OA Status:Closed
Free access at:Official URL. An embargo period may apply.
Publisher DOI:https://doi.org/10.1109/ISCAS.2017.8050422
Official URL:http://ieeexplore.ieee.org/document/8050422/

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