Research in neuroscience suggests that networks of biological neurons undergo a constant reconfiguration of their topology via activity-dependent plasticity mechanisms. The observed growing and retracting of dendritic spines can be hypothesized to be a resource-optimizing strategy that limits the amount of energy spent on maintaining a large number synapses that are not contributing to the networks performance. Neuromorphic analog VLSI emulates biophysical processes of neural tissue using CMOS transistors operated in the sub-threshold regime, to achieve high energy efficiency. One of the constraints that limits the scalability of neuromorphic information processing architectures is the number of available synapse-emulating circuits, which is naturally limited by the integrated circuits (ICs) layout dimensions. Here we explore the possibility to exploit structural plasticity as a biologically-inspired strategy for optimizing resource usage in neuromorphic processors. We propose a mechanism that allocates the limited number of synapses during runtime, in order to choose event-sources that best contribute to the postsynaptic neurons activity. In this context, we show that neuronal activity can serve as an indicator of what synapse to connect to which source, mimicking activity dependent dynamics of dendritic spines and making optimal allocation of the resources available on the neuromorphic hardware.