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Digital multiplier‐less implementation of high‐precision SDSP and synaptic strength‐based STDP


Asgari, Hajar; Maybodi, Babak Mazloom‐Nezhad; Sandamirskaya, Yulia (2020). Digital multiplier‐less implementation of high‐precision SDSP and synaptic strength‐based STDP. International Journal of Circuit Theory and Applications, 48(5):724-738.

Abstract

Spiking neural networks (SNNs) can achieve lower latency and higher efficiency compared with traditional neural networks if they are implemented in dedicated neuromorphic hardware. In both biological and artificial spiking neuronal systems, synaptic modifications are the main mechanism for learning. Plastic synapses are thus the core component of neuromorphic hardware with on‐chip learning capability. Recently, several research groups have designed hardware architectures for modeling plasticity in SNNs for various applications. Following these research efforts, this paper proposes multiplier‐less digital neuromorphic circuits for two plasticity learning rules: the spike‐driven synaptic plasticity (SDSP) and synaptic strength–based spike timing–dependent plasticity (SSSTDP). The proposed architectures have increased the precision of the plastic synaptic weights and are suitable for spiking neural network architectures with more precise calculations. The proposed models are validated in MATLAB simulations and physical implementations on a field‐programmable gate array (FPGA).

Abstract

Spiking neural networks (SNNs) can achieve lower latency and higher efficiency compared with traditional neural networks if they are implemented in dedicated neuromorphic hardware. In both biological and artificial spiking neuronal systems, synaptic modifications are the main mechanism for learning. Plastic synapses are thus the core component of neuromorphic hardware with on‐chip learning capability. Recently, several research groups have designed hardware architectures for modeling plasticity in SNNs for various applications. Following these research efforts, this paper proposes multiplier‐less digital neuromorphic circuits for two plasticity learning rules: the spike‐driven synaptic plasticity (SDSP) and synaptic strength–based spike timing–dependent plasticity (SSSTDP). The proposed architectures have increased the precision of the plastic synaptic weights and are suitable for spiking neural network architectures with more precise calculations. The proposed models are validated in MATLAB simulations and physical implementations on a field‐programmable gate array (FPGA).

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Additional indexing

Item Type:Journal Article, refereed, original work
Communities & Collections:07 Faculty of Science > Institute of Neuroinformatics
Dewey Decimal Classification:570 Life sciences; biology
Scopus Subject Areas:Physical Sciences > Electronic, Optical and Magnetic Materials
Physical Sciences > Computer Science Applications
Physical Sciences > Electrical and Electronic Engineering
Physical Sciences > Applied Mathematics
Uncontrolled Keywords:Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials, Applied Mathematics, Computer Science Applications
Language:English
Date:1 May 2020
Deposited On:16 Feb 2021 09:34
Last Modified:17 Feb 2021 21:02
Publisher:Wiley-Blackwell Publishing, Inc.
ISSN:1097-007X
OA Status:Closed
Publisher DOI:https://doi.org/10.1002/cta.2753

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