We present an automated design approach that leverages the commonly available digital design tools in order to rapidly synthesize asynchronous event-based interface circuits from behavioral VHDL code. As part of the proposed design approach, we describe a verification methodology that is able to reveal early in the design process potential timing failures in the generated circuits. Due to the fast design cycle, the approach presented allows designers to quickly explore different architectures for asynchronous circuits and compare them using quantitative metrics based for example on power consumption or silicon area. We validated the proposed design method by synthesizing asynchronous interface circuits for a neuromorphic multi-neuron architecture, and fabricating the VLSI device. We present data from silicon that demonstrates the correct operation of the automatically generated circuits.